1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating such semiconductor device, and more specifically to a semiconductor device having a multilevel interconnection for electrically connecting a plurality of conduction layers through connection holes formed in an insulation layer and a method of fabricating such a semiconductor device.
2. Description of Related Art
With the development of higher integration density and performance of LSIs (Large Scale Integrated Circuits), device dimensions are increasingly miniaturized and devices are multi-layered. In order to reduce ever increasing wiring delay due to miniature multi-layered wiring, it is necessary to scale with appropriate ratios such parameters, for example, wiring film thickness which affect wiring resistance and capacity, a film thickness between layers and a relative dielectric constant which affect wiring capacitance, and a wiring resistivity which affects wiring resistance and the like.
As for wiring materials, it is preferable to a have a lower resistivity so as to transmit electrical signals without large voltage drop. Metals like gold (Au), copper (Cu) and silver (Ag) exhibit lower resistivity than aluminum (Al) which has been widely used. It is reported that among other metals, copper has a higher melting point than aluminum and higher activation energy to cause the electro-migration phenomenon, thereby improving reliability as compared to aluminum. However, in order to use copper as miniature wiring, since there is no suitable gas to perform dry etching on the insulation film having a copper underlayer with high selectivity ratio, buried wiring is generally formed by utilizing the Damascene technique. In particular, the dual-damascene technique in which both connection holes and wiring are buried is effective from the viewpoints of expanding alignment margin in lithography and shortening fabrication processing.
Also, it is preferable that an insulation layer has a smaller relative dielectric constant in order to reduce wiring capacitance. Materials to be used are shifting to a low relative dielectric constant materials represented by allyl ether resin, SiOC and the like. However, the low relative dielectric constant materials such as allyl ether resin have lower Young's modulus than a SiO2 film or SiO2 film containing fluorine used in the related art, thereby providing relatively less dense films.
FIG. 10 is a diagrammatic cross section view of a part of a semiconductor device in the related art. An insulation film 2 is formed on the upper surface of a semiconductor substrate 1. Formed on a part of the upper surface of the insulation film 2 are wiring grooves in which a first conductive layer 3 and a second conductive layer 4 are formed. A diffusion protection film 5 is formed on the upper surface of the insulation film 2 on which the first conductive layer 3, and the second conductive layer 4 are formed and an insulation film 6 is formed on the upper surface of the diffusion protection film 5. A third conductive layer 8 is formed in a wiring groove which is formed on a part of the upper surface of the insulation film 6. A diffusion protection film 9 is formed on the insulation film 6 on which the third conductive layer 8 is formed. An insulation film 10 is formed on the upper surface of the diffusion protection film 9. Additionally, the first conductive layer 3, the second conductive layer 4 and the third conductive layer 8 are electrically interconnected by way of opening portions 7. It is to be noted here that the same material as the third conductive layer 8 is filled in the opening portions. The diffusion protection films 5, 9 may be eliminated depending on the layer structure and the material of the conductive layers. Device areas and device isolation areas to be formed on the semiconductor substrate 1 are not shown in the drawing.
As a method of fabricating a semiconductor device as described hereinabove, it is known to form an interlayer insulation film on a substrate, to form upper layer wiring and lower layer wiring on the substrate, to form plugs for electrically connecting the upper layer wiring and lower layer wiring, and to form poles in the interlayer insulation film adjacent to the plugs, wherein the poles are not constituting an electrically conductive path {for example, see Japanese Patent Application Publication No. 11-154679 (pages 3-7, FIG. 1-FIG. 10)}.